1Hz-to-440Hz Transistor Phase-Locked Loop

I built a phase-locked loop out of discrete transistors and diodes. It takes a 1Hz square wave reference and produces a 440Hz tone (musical note A4).

Demonstration

Physical Hardware

The PLL is built on a two-layer 0.8mm copper clad board. I made vias by drilling 0.5mm holes and soldering cut off leads on each side.

Schematic walkthrough

You can find a PDF of the full schematic and block diagram here.

Voltage-Controlled Oscillator

The VCO is a conventional transistor astable multivibrator. The base resistors are split into a pair of high-valued bias resistors to set the lowest frequency when the control voltage is zero and a pair of resistors connected to the control voltage to raise the frequency as the control voltage increases. The tuning range is about 340Hz to 645Hz. The PLL is able to lock for any output frequency in the VCO range.

Frequency Divider

I had a lot of fun playing with different types of frequency dividers, but I eventually settled on a conventional binary counter. One alternative I looked at was US3569864A, which uses essentially an injection-locked oscillator that selects the division of its input frequency that is closest to its natural oscillation frequency, which allows dividers greater than two and therefore fewer components. The downside is it is only accurate with a narrow input frequency range since it will lock to a different division ratio if the input frequency changes a lot. There are other options, but a binary counter is pretty foolproof.

Flip-flop

I used a popular topology for a discrete toggle flip-flop. Two of the bits have an extra diode for an asynchronous preset.

Starting with Q high and /Q low, Q20 is on and Q21 is off. The cathode of D21 is pulled high. The cathode of D21 is pulled down by R43, but it will be forward biased since the base of Q20 is also on. When a negative edge is applied to the clock line, the capacitors cause negative pulses on their opposite ends. On the D21 side, nothing much happens since it remains reverse biased. However, for the D20 side, the negative pulse is also applied to the base of Q20, turning it off and allowing Q21 to turn on. As the pulse on Q20 decays, Q21 turns on and Q20 remains off, and the flip-flop has toggled.

Counting to 440

The first six bits of the counter divide by 55, and three following flip-flops divide by an additional 8 to get to 440. For the divide-by-55 counter, a DTL NAND gate presets the six lowest flip-flops when the value reaches 54. Since the flip-flops are triggered by negative clock edges, resetting to zero would cause succeeding flip-flops to be triggered.

Phase Detector

This is a phase frequency detector (see Analog Devices MT-086). It consists of two RS latches, a NAND gate, and a charge pump with a switched current source and sink. It takes a little more hardware than a XOR-based phase detector, but it will always push the control in the right direction regardless of how far away the frequency is.

If the reference edge arrives first, the UP signal will turn on the high-side current source and speed up the ouput clock to match the reference. Once the output edge arrives, both UP and DOWN are on, which triggers the NAND gate to reset both latches. In this way, the change in the control signal is proportional to the phase error. If the opposite happens and the output edge arrives first, the DOWN signal will turn on the low-side current source and slow down the output clock. If both edges arrive at the same time, the control voltage will stay the same since the clocks are phase locked.

The output of the NAND gate has a small filter to make it more resistant to glitches and keep the reset signal low long enough for both latches to reset. The current sources are about 5µA each, which is small enough to keep the loop filter values practical but large enough that leakages aren’t very significant.

Loop filter

PLL loop filter design can be complicated. There are lots of tradeoffs to be made in lock time and jitter and other factors. Here are a couple references for all the details:

What finally got me a usable filter was the design procedure in this Stack Exchange answer.

Intuitively, some capacitance is needed to maintain the control voltage and to prevent small phase errors from causing big control changes. Combined with the larger capacitor with a series resistor, a phase difference will have a large control impact during the time that one of the current sources is on, but during the part of the cycle that both current sources are off, the larger capacitor will bring the control voltage back down, with only a small impact on the long-term control voltage. This allows the loop to correct for a phase error without affecting the long-term frequency much. From a loop stability perspective, the series RC adds a zero to boost the phase near the gain crossing and improve stability.

My filter response looks something like the above simulation plot, although I am not sure where exactly the gain crossing is. Based on the overshoot in the resulting transient response, I expect it is a little to the left or right of the phase peak, but I wasn’t able to improve it much by adjusting the filter components.

The extra low-pass pole of R98 and C35 is set above the gain crossing to avoid impacting the phase margin, but it still helps prevent sudden changes in frequency. The output of the filter is buffered with a MOSFET so that the oscillator doesn’t discharge the loop filter capacitors. There is also a 1µF capacitor on the control signal near the oscillator.

This is a screenshot of the control voltage as the PLL locks to a newly-applied 1Hz reference signal. It overshoots some, but it gets a pretty good lock in about 20 seconds. After letting it run for a minute or so, the tuner app on my phone shows the output oscillating (in time with the 1Hz reference) within about ±0.15Hz of 440Hz. Which is ±340ppm, but not too bad.

Lock detect

When the loop achieves phase lock, neither the UP nor the DOWN signals will be on for a long time, so a NOR gate with a big filter provides an analog lock detect. A comparator turns on the LED when the lock detect signal rises high enough. The gain of the comparator isn’t very large and the input rises very slowly, so the LED still fades in and out visibly.

Sine wave filter

Since this PLL is designed for only a single frequency, an easy way to get a clean sine wave is to aggressively filter the square wave output. I used a 3rd-order Chebyshev low-pass filter, designed with the help of TI’s Webench filter design tool. The first stage is an RC low-pass, with the resistor split into a divider to achieve the best offset and amplitude for the succeeding stages. After a buffer, a Sallen-Key filter provides two additional poles. The result is a pretty clean sine wave to be fed to the amplifier.

The second and third harmonics are 36dB-40dB down from the fundamental. The total harmonic distortion (THD) calculated from the crude FFT below is around 2%-3%.

Audio amplifier

The audio amplifier is a class AB emitter follower design with a driver transistor biased with feedback from the output. I added R94 since the speaker I was using was louder than I expected. The MPSA56 in TO-92 is just because I didn’t have any surface mount PNPs on hand.